1. Field of the Invention
The present invention relates to a light emitting diode (LED) array employable in an electronic printer for photolithography, and particularly to the structure of a plurality of interconnection conductors in the LED array.
2. Description of the Related Art
FIG. 8 is a schematic top plan view showing light emitting diodes (LEDs) 10 in a portion of a prior art LED array 12. FIG. 9 is a cross-sectional view taken along line 9xe2x80x949 of FIG. 8.
The process of fabricating the prior art light emitting diode array 12 is as follows:
First, an Al2O3 layer 14 acting as a diffusion prevention layer is formed in a N-GaAs substrate 16. Then, an insulating layer 18 such as Si3N4 is formed on the Al2O3 layer 14. Then, a P-type impurity such as Zn is diffused into portions of the surface of the N-GaAs substrate 16 that are not covered by the Al2O3 layer 14 and the insulating layer 18 by the vapor diffusion method. As a result, p-GaAsP regions 20 are formed in the N-GaAs substrate 16. The regions 20 act as light emitting areas. Then, interconnection conductors 22 are formed. The interconnection conductors 22 are in ohmic contact with the p-GaAsP regions 20, and extend from the regions 20 over stepped portions 24 to the top surface of the insulating layer 14. In this application, a xe2x80x9cstepped portionxe2x80x9d of a conductor refers to a portion of the conductor where its height or level changes abruptly in one or more steps.
It is an object of the present invention to provide a light emitting diode array that is able to free from a disconnection due to a current concentration without sacrificing the light outputting efficiency of the LED array.
It is another object of the present invention to provide a light emitting diode array having a reduced area and thus a reduced cost.
It is another object of the present invention to provide a light emitting diode array in which the outer interconnection conductors are located close to the locations where the die of the array is cut from a semiconductor slice. Therefore, a reduction in the area of the light emitting diode array die can be achieved and a margin for cutting the die can be secured.
It is another object of the present invention to provide a light emitting diode array that is able to prevent a direct influence of an electric field at the transition from a wide-width segment of an interconnection-conductor to a narrow-width segment of the interconnection conductor.
According to one aspect of the present invention, there is provided a light emitting diode array comprising a semiconductor substrate; a diffusion prevention layer formed on the semiconductor substrate, the diffusion prevention layer having a hole which exposes the light emitting region and having an edge that is spaced apart from the hole; an insulating layer formed on the diffusion prevention layer, the insulating layer having a level drop at the edge of the diffusion prevention layer; and an interconnection conductor which extends on the insulating layer and which has a stepped portion at the level drop of the insulating layer, the interconnection conductor including a wide-width segment and a narrow-width segment which is in ohmic contact with the light emitting region, the stepped portion of the interconnection conductor being located in the wide-width segment.
The wide-width segments of the interconnection conductor may be asymmetrical with respect to the path of the interconnection conductor, and protrude away from the nearest edge of the die.
The interconnection conductor may have a border with curved or arcuate portions where the wide-width segment joins the narrow-width segment (or more than one narrow-width segment).
The present invention is also directed to a method of forming a light emitting diode array.
It is an object of the present invention to provide a method of forming a light emitting diode array that is able to reduce the risk that an interconnection conductor might be cut by etchant which gathers at a stepped portion of the interconnection conductor during a patterning step of the interconnection conductor.
It is another object of the present invention to provide a method which is able to reduce the area of a light emitting diode array die, and therefore reducing costs.
It is another object of the present invention to provide a method of forming a light emitting diode array which has low contact resistance at the light emitting regions by using AuBe or AuZn.
According to one aspect of the present invention, there is provided a method of forming a light emitting diode array, comprising the steps of providing a semiconductor substrate; forming a diffusion prevention layer on the semiconductor substrate, the diffusion prevention layer having an edge; forming a hole in the diffusion prevention layer at a position that is spaced apart from the edge of the diffusion prevention layer; forming a light emitting regions on the substrate beneath the hole; forming an insulating layer on the diffusion prevention layer, the insulating layer having a level drop at the edge of the diffusion prevention layer, the insulating layer additionally having a hole which is aligned with the hole in the diffusion prevention layer; covering the light emitting region and the insulating layer with a conductive layer, the conductive layer having a stepped portion at the level drop of the insulating layer; forming a mask layer on a predetermined portion of the conductive layer, the mask layer having a wide-width segment located over the stepped portion and a narrow-width segment which extends over the light emitting region; and selectively forming an interconnection conductor by etching the conductive layer using the mask layer.
According to another aspect of the present invention, there is provided a method of forming a light emitting diode array, comprising the steps of providing a semiconductor substrate; forming a diffusion prevention layer on the semiconductor substrate, the diffusion layer having an edge; forming a hole in the diffusion prevention layer at a position that is spaced apart from the edge of the diffusion prevention layer; forming a light emitting region on the substrate beneath the hole; forming an insulating layer on the diffusion prevention layer, the insulating layer having a level drop at the edge of the diffusion prevention layer, the insulating layer additionally having a hole which is aligned with the hole in the diffusion prevention layer; covering the light emitting region and the insulating layer with a thick conductive layer which has a recess that is aligned with the holes; forming a first mask layer on a first predetermined portion of the conductive layer, the first predetermined portion being located adjacent the recess in the conductive layer; conducting a first etching step to reduce the thickness of the conductive layer except beneath the first mask layer; removing the first mask layer; forming a second mask layer on a second predetermined portion of the conductive layer, the second mask layer having a wide-width segment located over the stepped portion and a narrow-width segment which extends over the light emitting region; and selectively forming an interconnection conductor by etching the conductive layer using the second mask layer.
According to another aspect of the present invention, there is provided a method of forming a light emitting diode array, comprising the steps of providing a semiconductor substrate; forming a diffusion prevention layer on the semiconductor substrate, the diffusion prevention layer having an edge; forming a hole in the diffusion prevention layer at a position that is spaced apart from the edge of the diffusion prevention layer; forming a light emitting region on the substrate beneath the hole; forming an insulating layer on the diffusion prevention layer, the insulating layer having a level drop at the edge of the diffusion prevention layer, the insulating layer additionally having a hole which is aligned with the hole in the diffusion prevention layer; selectively forming a staircase element having a lower portion which contacts the light emitting region and an upper portion which contacts the insulating layer, the staircase element being made of a first metal; covering the insulating layer, the staircase element, and the light emitting region with a layer of a second metal which has a faster etch rate than the first metal; forming a mask layer on a predetermined portion of the conductive layer; and selectively forming an interconnection conductor by etching the layer of the second metal using the mask layer. Here, the first metal layer may comprise AuBe or AuZn and the second metal layer may comprise Al.